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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 512K X 16 bit
DESCRIPTION
BS616LV8011
* Very low operation voltage : 2.7 ~ 3.6V * Very low power consumption : Vcc = 3.0V C-grade: 40mA (Max.) operating current I-grade : 50mA (Max.) operating current 1uA (Typ.) CMOS standby current * High speed access time : -70 70ns (Max.) at Vcc=3.0V -10 100ns (Max.) at Vcc=3.0V * Automatic power down when chip is deselected * Three state outputs and TTL compatible * Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE1,CE2 and OE options
The BS616LV8011 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable(CE1,CE2) and active LOW output enable(OE) and three-state output drivers. The BS616LV8011 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8011 is available in 48-pin BGA package.
PRODUCT FAMILY
SPEED (ns)
Vcc=3.0V
PRODUCT FAMILY
OPERATING TEMPERATURE +0 O C to +70 O C -40 O C to +85 O C
Vcc RANGE 2.7V ~ 3.6V 2.7V ~ 3.6V
POWER DISSIPATION STANDBY Operating
(ICCSB1, Max) Vcc=3.0V (ICC, Max) Vcc=3.0V
PKG TYPE
BS616LV8011AC BS616LV8011AI
70 / 100 70 / 100
16uA 24uA
40mA 50mA
BGA-48-0608 BGA-48-0608
PIN CONFIGURATIONS
1 A B C D E F G H X D8 D9 VSS VCC D14 D15 A18 2 OE X D10 D11 D12 D13 NC . A8 3 A0 A3 4 A1 A4 5 A2 6 CE2 D0 D2 VCC VSS D6
BLOCK DIAGRAM
A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096
CE1 D1 D3 D4 D5
A5 A17 Vss A14 A12 A9
A6 A7 A16 A15 A 13 A10
4096 D0 16 Data Input Buffer 16 Column I/O
. . . .
D15
. . . .
Write Driver
Sense Amp 256 Column Decoder
16
Data Output
16
Buffer
CE1 CE2
16 Control Address Input Buffer
WE A11
D7 NC .
OE WE
A11 A10 A9 A8 A7 A6 A5 A18 Vcc Gnd
48-Ball CSP top View
X: Don't care
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8011
1
Revision 2.3 April 2002
BSI
PIN DESCRIPTIONS Name
A0-A18 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
BS616LV8011
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
WE Write Enable Input
OE Output Enable Input
D0 - D15 Data Vcc Gnd
Input/Output Ports
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read Write CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X D0~D7 High Z High Z Dout Din D8~D15 High Z High Z Dout Din Vcc CURRENT ICCSB , I CCSB1 ICC ICC ICC
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL VTERM TBIAS TSTG PT IOUT PARAMETER
Terminal Voltage Respect to GND with
OPERATING RANGE
UNITS
V
O
RATING
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70O C -40O C to +85OC
Vcc
2.7V ~ 3.6V 2.7V ~ 3.6V
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
O
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS616LV8011
CIN CDQ
PARAMETER Input Capacitance Input/Output Capacitance
CONDITIONS
MAX.
UNIT
VIN=0V VI/O=0V
10 12
pF pF
1. This parameter is guaranteed and not tested.
2
Revision 2.3 April 2002
BSI
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER NAME
VIL VIH IIL IOL VOL VOH ICC
BS616LV8011
TEST CONDITIONS
Vcc=3V Vcc=3V
PARAMETER
Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current
MIN.
-0.5 2.0 --Vcc=3V Vcc=3V
TYP. (1)
--------
MAX.
0.8
Vcc+0.2
UNITS V V uA uA V V mA
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH , or CE2 = ViL, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL = 2mA Vcc = Min, IOH = -1mA Vcc=max, CE1=VIL and CE2= VIH, IDQ = 0mA, F = Fmax(3) Vcc= max, CE1 = VIH or CE2 = VIL, IDQ = 0mA Vcc= max,CE1 Vcc-0.2V, or CE2 0.2V, VIN Vcc-0.2V or VIN 0.2V
1 1 0.4 -40
-2.4 --
Vcc=3V
ICCSB
Standby Current-TTL
Vcc=3V
--
--
1
mA
ICCSB1
Standby Current-CMOS
Vcc=3V
--
1
16
uA
1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC .
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )
SYMBOL
V DR
PARAMETER
Vcc for Data Retention CE1 V IN CE1 V IN
TEST CONDITIONS
Vcc - 0.2V or CE2 0.2V or Vcc - 0.2V or VIN 0.2V Vcc - 0.2V or CE2 0.2V Vcc - 0.2V or VIN 0.2V
MIN.
1.5
TYP. (1)
--
MAX.
--
UNITS
V
ICCDR tCDR tR
Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
-0 TRC (2)
0.8 ---
12 ---
uA ns ns
See Retention Waveform
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VIH
Vcc
VDR
1.5V
Vcc
t CDR
CE1 Vcc - 0.2V
tR
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
VDR
1.5V
Vcc
t CDR
tR
CE2 0.2V
CE2
VIL
VIL
R0201-BS616LV8011
3
Revision 2.3 April 2002
BSI
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns 0.5Vcc
WAVEFORM
BS616LV8011
KEY TO SWITCHING WAVEFORMS
INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
AC TEST LOADS AND WAVEFORMS
3.3V OUTPUT
100PF
INCLUDING JIG AND SCOPE
1269
3.3V OUTPUT
1269
,
5PF 1404
INCLUDING JIG AND SCOPE
1404
FIGURE 1A
THEVENIN EQUIVALENT 667 ALL INPUT PULSES
FIGURE 1B
OUTPUT
1.73V
Vcc GND
10%
90% 90%
10%
5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=3V )
READ CYCLE
JEDEC PARAMETER PARAMETER NAME NAME
DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) (CE1) (CE2)
BS616LV8011-70 MIN. TYP. MAX.
BS616LV8011-10 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV t ELQV1 t ELQV2 tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX
tRC tAA t ACS1 t ACS2 tOE tCLZ tOLZ tCHZ tOHZ tOH
70 ----10 10 0 0 10
-----------
-70 70 70 35 --40 35 --
100 ----15 15 0 0 15
-----------
-100 100 100 50 --45 40 --
Output Enable to Output in Low Z Chip Deselect to Output in High Z(CE2,CE1) Output Disable to Output in High Z Output Disable to Address Change
R0201-BS616LV8011
4
Revision 2.3 April 2002
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
BS616LV8011
t RC t AA t OH
t OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t ACS2 t ACS1
CE1
t CLZ
D OUT
(5)
t
CHZ
(5)
READ CYCLE3 (1,4)
ADDRESS
t RC
t AA
OE
t OE
CE2
t
OH
t ACS2 t OLZ t ACS1 t
(5) CLZ
CE1
t OHZ (5)
(1,5) t CHZ
D OUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested.
R0201-BS616LV8011
5
Revision 2.3 April 2002
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=3V )
WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME
BS616LV8011-70 MIN. TYP. MAX.
BS616LV8011
DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1,CE2,WE) BS616LV8011-10 MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns
tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHOX
t WC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW
70 70 0 70 35 0 0 30 0 0 5
------------
------30 --30 --
100 100 0 100 50 0 0 40 0 0 10
------------
------40 --40 --
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1)
ADDRESS
t WC
t
OE
(3)
WR
CE2
(5)
t CW
CE1
(5)
(11)
t AW
WE
(3)
t AS
(4,10)
t
WP
(2)
t OHZ
D OUT
t t DW
DH
D IN
R0201-BS616LV8011
6
Revision 2.3 April 2002
BSI
WRITE CYCLE2 (1,6)
BS616LV8011
t
WC
ADDRESS
CE2
(11)
CE1
(5)
t
CW
t AW
WE
t t WP
(2)
WR
(3)
t AS
(4,10)
t DH
(7) (8)
t WHZ
D OUT
t DW t DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8011
7
Revision 2.3 April 2002
BSI
ORDERING INFORMATION
BS616LV8011
BS616LV8011
XX
-- Y Y
SPEED 70: 70ns 10: 100ns
GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE A :BGA - 48 PIN(6x8mm)
PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616LV8011
E1
8
Revision 2.3 April 2002
BSI
REVISION HISTORY
Revision
2.2 2.3
BS616LV8011
Description
2001 Data Sheet release Modify some AC parameters
Date
Apr. 15, 2001 April,11,2002
Note
R0201-BS616LV8011
9
Revision 2.3 April 2002

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